4432-T-B1 B 915【PDF 18/47 页】KIT DEV TEST EZRADIOPRO SI4432

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Si4430/31/32-B1

Rev 1.1

3. Controller Interface

3.1. Serial Peripheral Interface (SPI)

The Si4430/31/32 communicates with the host MCU over a standard 3-wire SPI interface: SCLK, SDI, and nSEL.

The host MCU can read data from the device on the SDO output pin. A SPI transaction is a 16-bit sequence which

consists of a Read-Write (R

/W) select bit, followed by a 7-bit address field (ADDR), and an 8-bit data field (DATA)

as demonstrated in Figure 3. The 7-bit address field is used to select one of the 128, 8-bit control registers. The

/W select bit determines whether the SPI transaction is a read or write transaction. If R

/W = 1 it signifies a WRITE

transaction, while R

/W = 0 signifies a READ transaction. The contents (ADDR or DATA) are latched into the

Si4430/31/32 every eight clock cycles. The timing parameters for the SPI interface are shown in Table 10. The

SCLK rate is flexible with a maximum rate of 10 MHz.

Figure 3. SPI Timing

To read back data from the Si4430/31/32, the R/W bit must be set to 0 followed by the 7-bit address of the register

from which to read. The 8 bit DATA field following the 7-bit ADDR field is ignored on the SDI pin when R/W = 0. The

next eight negative edge transitions of the SCLK signal will clock out the contents of the selected register. The data

read from the selected register will be available on the SDO output pin. The READ function is shown in Figure 4.

After the READ function is completed the SDO pin will remain at either a logic 1 or logic 0 state depending on the

last data bit clocked out (D0). When nSEL goes high the SDO output pin will be pulled high by internal pullup.

Table 10. Serial Interface Timing Parameters

Symbol

Parameter

Min (nsec)

Diagram

Clock high time

Clock low time

Data setup time

Data hold time

Output data delay time

Output enable time

Output disable time

Select setup time

Select hold time

Select high period

nSEL

SCLK

SDI

MSB

LSB

A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

xx xx

RW A7

A6 A5

Data

Address

SDI

SCLK

nSEL

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